Cadambi, Srihari Goldstein, Seth C. Efficient Place and Route for Pipeline Reconfigurable Architectures In this paper, we present a fast and efficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, and fairly efficient. We represent pipeline reconfigurable architectures by a generalized VLIW-like model. The complex architectural constraints are effectively expressed in terms of a single graph parameter: the routing path length (RPL). Compiling to our model using RPL, we demonstrate fast compilation times and show speedups of between 10x and 200x on a pipeline reconfigurable architecture when compared to an UltraSparc-II computer sciences 1984-01-01
    https://kilthub.cmu.edu/articles/journal_contribution/Efficient_Place_and_Route_for_Pipeline_Reconfigurable_Architectures/6605102
10.1184/R1/6605102.v1