Coupled Oscillator Networks for Computation in the Beyond-CMOS Era

CMOS technology and the aggressive roadmap outlined by the Moore’s law enabled today’s powerful computers and smartphones. Traditional scaling of CMOS technology is
reaching an end due to a number of factors including cost and fundamental physical limits such as increased leakage current and high stochastic variation. In the meantime, the
nature of computation also changed. The exchange and processing of graphical data increased, big data and IoT arrived. These more data-centric applications exacerbate the
power consumption due to intense memory access required in the traditional von Neuman computation scheme. Therefore, to overcome these problems we need not only new devices or computation schemes; but a co-design of alternative compute paradigms and the device fabric that will enable them. This work proposes using coupled oscillator networks for computation. These systems mimic the parallelism of the brain to overcome the von Neumann bottleneck. The device fabric we explore is the S-type negative differential resistance (S-NDR) oscillator, whose
unique device properties lends itself to area and power efficient, BEOL compatible dense arrays. We explore the device-circuit relations of S-NDR devices, develop nano-oscillators and integrate them with the existing scaled CMOS technology. Using a compact circuit model and SPICE simulations, we show that capacitively coupled networks of S-NDR oscillators can solve image processing problems such as edge detection, stereo vision and
image segmentation. To verify the capabilities of oscillator networks on hardware, we design and tape-out
a CMOS oscillator network. We analyze the capacitive coupling scheme of oscillators and extend Kuramoto’s model to capture the properties of capacitive coupling. We finally demonstrate an image segmentation engine utilizing the oscillator network.