S-type Negative Differential Resistance: Emerging Memory and Oscillators for Next-Generation Computation

2015-12-01T00:00:00Z (GMT) by Abhishek A. Sharma
Increasing data-centric nature of compute has motivated the need for overcoming the von Neumann memory-access bottleneck. Multi-functional beyond-CMOS have shown a great potential in uniquely complementing and augmenting the compute capability by utilizing emerging paradigms like on-chip memory and brain-inspired computing. In this work, we focus on first understanding the physics of devices that show S-type negative differential resistance behavior (S-NDR) and then engineering them for use in emerging memory (RRAM, selectors) and compute (oscillators for simulated annealing, neural networks, physically obfuscated keys) architectures. To understand the electro-thermal dynamics of filament formation in metal semiconductor/oxide
-metal (MSM) stacks, we first develop a novel high-speed transient thermometry. This reveals a two-step current localization and nucleation process that is responsible for forming or threshold switching in these MSM stacks. This current localization event manifests as S-NDR in these
devices, which we explore to variously understand threshold switching and oscillatory behavior. We also apply the developed nano-scale thermometry to resistive switching memory devices to extract the role of temperature in the switching process. After establishing self-consistency with
microstructural changes under a TEM, we estimate the filament size and evolution with bias and current compliance.