file.pdf (2.9 MB)
Download file

Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory

Download (2.9 MB)
journal contribution
posted on 01.09.2014, 00:00 authored by Fazle Sadi, Berkin Akin, Doru T. Popovici, James C. Hoe, Larry Pileggi, Franz Franchetti

Real-time system level implementations of complex Synthetic Aperture Radar (SAR) image reconstruction algorithms have always been challenging due to their data intensive characteristics. In this paper, we propose a basis vector transform based novel algorithm to alleviate the data intensity and a 3D-stacked logic in memory based hardware accelerator as the implementation platform. Experimental results indicate that this proposed algorithm/hardware co-optimized system can achieve an accuracy of 91 dB PSNR compared to a reference algorithm implemented in Matlab and energy efficiency of 72 GFLOPS/W for a 8k×8k SAR image reconstruction.


Publisher Statement

© 2014IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.



Usage metrics