An Analysis of U.S. Patent #5,243,538 “Comparison and Verification System for Logic Circuits and Method Thereof"

On Sept. 7, 1993, U. S. Patent Number 5,243,538 was awarded to four Hitachi employees for a technique for comparing logic circuits using Binary Decision Diagrams (BDDs). Although the U. S. patent application was filed on Aug. 7, 1990, they had filed for a patent in Japan on Aug. 9, 1989, and hence this earlier date should be used in determining the prior art. The key property exploited by the patentees is that by generating the BDDs for the two logic circuits according to a unique ordering of the variables, the task of comparing the BDDs is greatly simplified. The patentees did not cite and apparently were not aware of work done on BDD-based logic comparison during the 9 years between the cited papers by S. B. Akers and their patent application. In particular, the author devised a technique for generating and comparing logic functions using Ordered (i.e., assuming a unique ordering of variables) BDDs in 1984. Papers published in 1985 (Design Automation Conference) and 1986 (IEEE Transactions on Computers) describe this method in detail. We assert that this patent should not have been issued, as it attempts to patent prior art.