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Automatic and hierarchical verification of asynchronous circuits using temporal logic

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posted on 2013-07-01, 00:00 authored by B Mishra, E. M. Clarke
Computer Science Department

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Publisher Statement

© ACM, 2013. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published at http://doi.acm.org/10.1145/2492045.2492054

Date

2013-07-01

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    Keywords

    Electronic circuit design.Information and Computing Sciences not elsewhere classified

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