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CMOS Circuit Verification with Symbolic Switch-Level Timing Simulation

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journal contribution
posted on 01.01.1986, 00:00 authored by Clayton B McDonald, Randal E. Bryant
Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically computing data-dependent Elmore delays. We present our symbolic simulation and delay calculation algorithms and discuss their application to the timing and functional verification of full-custom transistor-level CMOS circuitry


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