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Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation

journal contribution
posted on 1999-01-01, 00:00 authored by Manish Pandey, Randal BryantRandal Bryant
Institute for Software Research

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Date

1999-01-01

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    Keywords

    Formal VerificationSymbolic Trajectory EvaluationTransistor-LevelSwitch-LevelMemory ArraysSymmetryComputer Software not elsewhere classified

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    In Copyright

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