File(s) stored somewhere else

Please note: Linked content is NOT stored on Carnegie Mellon University and we can't guarantee its availability, quality, security or accept any liability.

Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis

journal contribution
posted on 01.01.1991, 00:00 by Randal BryantRandal Bryant

The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suitable for evaluation by conventional gate-level simulators and hardware simulation accelerators. TRANALYZE has the same generality and accuracy as switch-level simulation, generating models for a wide range of technologies and design styles, while expressing the detailed effects of bidirectional transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones generated by hand.

History

Publisher Statement

All Rights Reserved

Date

01/01/1991

Usage metrics

Exports