posted on 2003-11-28, 00:00authored bySeth C. Goldstein
Nanoscale technologies provide both challenges and
opportunities. We show that the issues and potential solutions
facing designers are technology independent and arise mainly
from shrinking device sizes and an increase in the number of
devices available. We explore how it is possible to use some of
the devices that will be available to help ease design complexity
as well as overcome process related challenges such as limited
layout freedom, increased defect densities, timing constraints, and
power dissipation.
History
Publisher Statement
This is a pre-copy-editing, author-produced PDF of an article accepted for publication in Journal of Logic and Computation following peer review. The definitive publisher-authenticated version Volume 13, Number 5, 2003 pp 639-688 is available online at: http://logcom.oxfordjournals.org/cgi/content/abstract/13/5/639