A RRAM Array for Logic-in-memory Applications

<p>  A modern computer mainly consists of two parts, processors and memory. Data is computed by processors and stored in memory before and after computing. With the increase of data-intensive applications like machine learning, data movement between memory and processors has been increased dramatically. The frequent data movement can induce large energy consumption and high delay which can limit the performance of large-data computing. One of the possible solutions to the problem lies in the compute-in-memory (CiM) architecture. In CiM architecture, data is processed at the place where it is stored and the amount of data commuting can be significantly reduced. </p> <p>In the recent twenty years, RRAM, as a type of emerging nonvolatile memories, has attracted large amount of attention in the CiM related applications. It has been widely reported that a RRAM cell can work as a non-volatile memory to store 1bit. In 2009, Borghetti and his colleagues demonstrated that RRAM can also be used for computing. They demonstrated a complete set of IMPLY-Reset logic using a 2-RRAM and 1- load circuit, showing the potential of RRAM in CiM applications. Later in 2014, Kavtinsky and his group moved one step further by proposing a more common NOR logic gate with a 3-RRAM circuit. </p> <p>Having understood the great potential of RRAM in computing, we tried to experimentally demonstrate both works. In our experiments, however, we found that both RRAM logic sets are susceptible to device constraints including limits on threshold voltage and resistance values. We designed a new set of RRAM logic called OSCAR which stands for optimized switching constraints for RACER. Our new logic set is less susceptible to the device constraints and more compatible with current RRAM technology. More importantly, we introduced an additional control voltage (Δ) to deal with the process variation between different RRAM devices. To demonstrate our work, we constructed arrays of RRAM logic gates consisting of a 1x4 RRAM arrays and an I/O interface made of an Arduino Uno and PCB. Using the memory array, we executed memory operations including SET, RESET and READ and CiM operation including OSCAR NOR. We showed that these logic gates are capable of both memory and CiM operations. We further studied the impact of device-to-device (D2D) variation and cycle-to-cycle (C2C) variation on the CiM operation. We found that the D2D variation is the dominant type of variation possibly due to the high variability in forming. We showed that the variations can cause the logic operations to fail. The device variations should be analyzed in detail to increase the success rate of RRAM logic. Although the process variation is large in our devices, the devices used for our experiments are 2µm X 2µm crossbars. The process variation might be reduced in smaller devices. </p> <pre><code><br></code></pre>