Embedded Machine Learning for Secure and Efficient Circuits and Systems

The evolution of machine learning (ML) enables its integration into a wide variety of applications. While ML’s potential for solving complex problems is well-documented, its deployment in low-level circuits and systems under strict power and area constraints remains a significant challenge. This dissertation focuses on extending ML’s impact on low-level embedded circuits and systems through an algorithm-hardware co-design approach.

The first part of this work explores how ML can replace traditional front-end hardware and algorithms in specific tasks with two examples: the application of decision tree ensembles for hard disk drive (HDD) data symbol detection, and the use of convolutional neural network (CNN) for neural spike sorting in implantable device. Both cases demonstrate efficient field-programmable gate array (FPGA) implementations that meet the requirements of embedded environments. Next, the dissertation explores innovative applications made feasible by ML, with a focus on RF fingerprinting—a physical layer authentication method for wireless communication security. This work demonstrates the successful classification of six transmitters using a Bayesian neural network, implemented with an innovative Gaussian random num ber generator. Additionally, the classification of 220 RF fingerprints generated by a single transmitter is accomplished using a high-performance CNN, implemented on low-power hardware. The performance of these systems is extensively validated under a wide range of signal-to-noise ratio (SNR) variations. The final part of the dissertation addresses the use of deep reinforcement learning (DRL) for integrated circuit control and functionality enhancement. It highlights how DRL can mitigate the degradation of wireless communication performance caused by temperature variations by controlling a reconfigurable power amplifier (PA) on the wireless transmitter. Moreover, DRL enables the restoration of temperature variation-induced RF fingerprint distortions using the reconfigurable PA. This control methodology is extended to voltage regulation in a single-inductor triple-output PMIC operating at cryogenic temper atures. A compact 0.45 mm2 DRL module is implemented, achieving 3.49 TOPS/W efficiency with a low latency of 4.925 µs for circuit control tasks. Its robust performance is demonstrated across a wide temperature range, from 358 K (85°C) to 4.2 K (-269°C).

Detailed algorithm-hardware co-design methodologies for these target applications are presented throughout the dissertation. The contributions of this work address challenges in integrating advanced deep learning capabilities within constrained embedded environments, providing insights for developing intelligent and efficient deep-learning-enabled integrated circuits and systems.