Integrated Circuit Test Optimization for Comprehensive Defect Characterization

The relentless scaling of integrated circuits (IC) are bringing challenges to the manufacturing process. The decreasing distance between transistors and complicated layout features leads to the occurrence of various types of manufacturing defects (shorts, missing material, etc.). These defects can cause a chip to malfunction, and therefore lead to an economic loss. Correctly identifying and understanding the characteristics of these defects is a key step in the development and optimization of a manufacturing process. Digital circuit testing serves as the basis for defect characterization in both yield ramping and high-volume production stages. This dissertation focuses on digital circuit testing because digital components typically comprise the main component in most modern ICs. It is the process of applying a set of test inputs (test sets/patterns) to the circuit under test, and observing the collected responses. After the responses are collected, diagnosis and physical failure analysis are deployed to find the root cause of these defects for ultimately improving the manufacturing process.

However, testing for defect characterization is not trivial, especially when both the circuit design and fabrication process are increasingly complex. The test set used may not be able to provide enough information for defect characterization. This is sometimes due to the time and memory constraints placed on testing, and sometimes because the test set used does not have sufficient "diagnosis power" (the ability to distinguish fault candidates). In addition, during yield ramping stage, the defects that could exist in the production chip may not be revealed using the production chip and conventional test procedure. In

this dissertation, four methods are developed to improve the test process to provide more information for better defect characterization. First, an adaptive test pattern reordering method is described for reducing test cost while preserving

diagnosis quality. An accurate diagnosis requires a sufficient amount of failing data. In practice, because of limited test time or tester memory, a commonly used practice is to only record the first few failing tests for a given failing chip. Once enough failing data is collected, the testing could terminate to save test time. The adaptive test pattern reordering work rearranges the test pattern order, so that more failing test

patterns can be collected with fewest number of applied test patterns. The framework borrows the idea from widely-used recommendation systems to “recommend" patterns to each individual chip under test. The adaptive pattern reordering is based on the kNN algorithm, and may suggest a different order for each failing chip. Second, an alternative way to perform adaptive test pattern reordering is developed to be used in cases where the design is very large and the tester memory is extremely limited, making the recommendation

system-based reordering approach impractical. The second reordering approach takes advantage of the clusters that exist in failing data, and suggests the order of each failing chip based on which cluster it belongs. Experiments utilizing the memory-constrained approach has shown to be as effective as the first reordering method, but with much smaller memory footprint. Third, when the test patterns available are not adequate for extracting sufficient information of the underlying defect, a dynamic approach to test generation for failure extraction is developed. Because conventionally the test set is generated for detecting, but not distinguishing different defects, these patterns are not optimal for pinpointing and characterizing a defect. The dynamic pattern generation method is developed to generate more patterns to exercise the defect multiple times and in multiple ways, so that more failing information is extracted. Newly created tests are derived using the real failing data that are collected during the testing. Sometimes a typical product design for a customer and its corresponding ATPG set for screening defects are not sufficient for comprehensively characterizing defects. This is especially true during the yield ramp of a new fabrication process. For this situation, it is better to utilize a test chip for characterizing defects in logic circuits. A test chip is a special type of chip designed to reveal defect mechanisms during

yield ramp, and the test chip usually comes with a special test technique. To achieve this goal, an algorithm to improve design efficiency of logic test chips is described. These test chips must reflect physical features of real designs well, and also be easily testable and diagnosable. Current design process involves solving an integer programming problem, which is very time-consuming. Two strategies are developed to efficiently solve the integer programming problem by making use of the underlying sparsity of test chip design. With this algorithm, the logic test chips design cycle is accelerated, and therefore reduces the total time required for defect characterization. The work discussed in this dissertation improves the test quality for defect characterization in different aspects. Two test pattern reordering work modifies the test application process and increases test efficiency. Dynamic test pattern generation work provides more information for diagnosis. Enhancement

to test chip design techniques accelerates yield ramping process. These works together improve the efficiency and effectiveness of digital circuit testing in the manufacturing process.