Modern Gate Array Design Methodology and Applications

The drive for electronics to be faster and consume less power motivates Integrated Circuit (IC) foundries to cram more transistors into silicon. As these process nodes have advanced, Application Specific Integrated Circuit (ASIC) manufacturing costs have skyrocketed [1–3]. In high-consequence applications such as industrial controllers, automobiles, aerospace, and defense, the increasingly complex and globalized IC manufacturing supply chain also brings many concerns due to resilience, Intellectual Property (IP) theft, counterfeiting, and tampering of an ASIC [4]. These fixed costs (often millions in USD) and supply chain risks prohibit many companies from taping out in leading edge process nodes [5,6]. General purpose ICs, such as Field Programmable Gate Arrays (FPGAs), are popular alternatives to avert high manufacturing costs and supply chain risks [7]. However, FPGAs have high per unit costs, and re-programmability introduces Power, Area, and Performance (PAP) overhead, security concerns, and mutability concerns. A Mask Configurable Gate Array (MCGA) is a gate array configured at manufacturing time via the Back End of Line (BEOL) mask set and can bridge the PAP, up front cost, and per unit cost gap between FPGAs and ASICs [8]. However, MCGAs have not been commercially viable due to design requirements that hamper process node portability.

This work proposes a modern MCGA design framework for advanced process nodes. By relying only on an industrial Electronic Design Automation (EDA) tool flow for synthesis and Place and Route (PnR) and by constructing the base fabric of the gate array with only foundry verified standard cells, is it portable across process nodes and has minimal PAP overheads compared to an ASIC. We call this a Foundational Cell-Array (FC-Array) design framework.

With the FC-Array design framework, we explore the design of a generalized gate array fabric in a 28nm planar CMOS process node and a 16nm FinFET process node. We show that the gate array fabric is compatible across a wide variety of design types. We test PAP of the FC-Array from 100 MHz to 1 GHz. In the 28nm process node at 100 MHz, the FC-Array increases power by 1.34× and area 1.94× on average compared to the standard cell ASIC. At 1 GHz, the FC-Array increases power by 1.85× and area 2.56× on average compared to a standard cell ASIC. In the 16nm process node at 100 MHz, the FC-Array increases average power and average area by 1.68× and 1.72×, respectively, compared to the standard cell ASIC. At 1 GHz, the general application iv FC-Array increases power by 1.56× and area by 1.85× on average compared to the standard cell ASIC. We compare the FC-Array on the 28nm planar CMOS process node and the 16nm FinFET process node against an embedded FPGA (eFPGA) taped out in a 16nm FinFET process node [9]. The eFPGA occupies 29× more area and consumes 17.8× more power than the 28nm FC-Array and occupies 103× more area and consumes 63× more power than the 16nm FC-Array.

With a practical framework for a completely new type of MCGA, we explore practical applications for the FC-Array. The FC-Array can effectively bring down the manufacturing cost per mm2 silicon in a 3nm process node by over 90%. Since the IP is not in a digital form, the FC-Array does not have mutability concerns and IP theft/tampering requires risky circuit editing compared to digital modification with an FPGA. When combined with 3D split manufacturing, the FC-Array Front End of Line (FEOL) base wafer gives no details about the underlying design, enabling an untrusted foundry to manufacture the base wafer without risk of IP theft or tampering. This FEOL base wafer can also be stockpiled, buffering potential supply chain concerns.

The FC-Array design framework resolves issues with difficult supply chain issues and high manufacturing costs associated with comparable performing ASICs. At the same time, FC-Array PAP is much closer to an ASIC performance. This ultimately enables a new avenue for taping out secure and high performance ICs with a lower power budget and at a more affordable cost.