On the Detection and Characterization of Elusive Logic Circuit Failures

<p dir="ltr">The rapid scaling of modern integrated circuits (ICs) is fundamental to the success of the electronics industry, but it also introduces complex defects that manifest from perturbations inherent to the fabrication process. During development, it is critical not only to identify these defects but also to characterize them to facilitate design and manufacturing improvements. </p><p dir="ltr">Manufacturing test, the primary method for identifying defective chips, applies test patterns generated by automatic test pattern generation (ATPG) tools. These tools derive efficient patterns based on logic circuit structure and assumptions about potential failure modes, known as fault models. When a defective chip is identified, software-based logic diagnosis analyzes the test responses to identify potential loca?tions of the underlying defect. Additionally, diagnosis may attempt to characterize the nature of the defect, again using fault models in one or more ways. </p><p dir="ltr">Diagnosis results from many chips can be collected to perform statistical analy?sis and identify trends in defect behavior. Furthermore, the outcomes of an individual diagnosis can guide physical failure analysis (PFA), a root-cause analysis that examines the physical structure and defect. </p><p dir="ltr">As design and manufacturing complexity continues to increase, so does the number of defects that cannot be represented by in-practice fault models, presenting a challenge to both test and diagnosis. This can lead to ineffective tests that fail to screen defective chips, as well as ambiguous or misleading diagnosis results that hinder effective PFA and broader yield analysis. Emerging technologies, such as backside power delivery, are expected to introduce issues that further challenge traditional PFA methods, thus increasing the need for diagnosis to even become more effective. </p><p dir="ltr">To address these challenges, fault models and diagnosis methodologies must evolve to provide more precise and actionable information. Instead of designing models that directly reflect all possible defect behaviors, this dissertation describes a more general technique that captures a wide range of these behaviors without requiring detailed knowledge of the underlying physical mechanisms. The methodology, called Pseudo-Exhaustive Physically-Aware Region (PEPR) testing, makes only broad assumptions about the nature of potential defects, namely that their effects can be bounded by a physical region. Additionally, PEPR is parameterizable, which allows tools and practitioners to adjust the region size to more precisely bound defects. </p><p dir="ltr">The demonstrated ability of PEPR to cover a wide range of defect behavior motivates its use in test generation. However, the physical and pseudo-exhaustive nature of PEPR presents challenges in test-pattern generation and fault-model integration, which this dissertation addresses. </p><p dir="ltr">Furthermore, the flexibility of PEPR enables precise and thorough defect char?acterization when integrated into the diagnosis process. This dissertation presents a PEPR-based diagnosis methodology called CHEF (CHaracterizing Elusive Logic Circuit Failures) that localizes defective behavior to precise physical regions that includes an exact boolean characterization of the fault behavior. Experiments on a set of failures from an industrial design show significant improvements over current commercial offerings. Additionally, CHEF provides precise descriptions of the faulty functionality introduced by defects, which enables a better understanding of defect mechanisms. </p><p dir="ltr">The contributions of this dissertation include the development of the PEPR methodology and an infrastructure to scale the methodology to industrial designs and methodology integration with commercial electronic design automation tools. Additionally, this dissertation presents the CHEF diagnosis methodology and an in?teractive diagnosis environment that allows for further characterization of defect be?havior, fault model creation based on observed defects, and diagnostic test pattern generation</p>