SRAM Reliability Improvement Using ECC and Circuit Techniques.pdf (2.93 MB)
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SRAM Reliability Improvement Using ECC and Circuit Techniques

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posted on 01.12.2014, 00:00 by Mark McCartney

Reliability is of the utmost importance for safety of electronic systems built for the automotive, industrial, and medical sectors. In these systems, the embedded memory is especially sensitive due to the large number of minimum-sized devices in the cell arrays. Memory failures which occur after the manufacture-time burnin testing phase are particularly difficult to address since redundancy allocation is no longer available and fault detection schemes currently used in industry generally focus on the cell array while leaving the peripheral logic vulnerable to faults. Even in the cell array, conventional error control coding (ECC) has been limited in its ability to detect and correct failures greater than a few bits, due to the high latency or area overhead of correction [43]. Consequently, improvements to conventional memory resilience techniques are of great importance to continued reliable operation and to counter the raw bit error rate of the memory arrays in future technologies at economically feasible design points [11, 36, 37, 53, 56, 70]. In this thesis we examine the landscape of design techniques for reliability, and introduce two novel contributions for improving reliability with low overhead. To address failures occurring in the cell array, we have implemented an erasurebased ECC scheme (EB-ECC) that can extend conventional ECC already used in memory to correct and detect multiple erroneous bits with low overhead. An important component of this scheme is the method for detecting erasures at runtime; we propose a novel ternary-output sense amplifier design which can reduce the risk of undetected read latency failures in small-swing bitline designs. While most study has focused on the static random access memory (SRAM) cell array, for high-reliability products, it is important to examine the effects of failures on the peripheral logic as well. We have designed a wordline assertion comparator (WLAC) which has lower area overhead in large cache designs than competing techniques in the literature to detect address decoder failure.




Degree Type



Electrical and Computer Engineering

Degree Name

Doctor of Philosophy (PhD)


Ken Mai